1. Field of the Invention
The present invention relates to analog to digital converters (ADC""s), and more particularly, to various topologies for high speed analog to digital converters that use interleaving of amplifier connections to reduce parasitic capacitance.
2. Related Art
A subranging analog to digital converter (ADC) architecture is suitable for implementing high-performance ADC""s (i.e. high speed, low power, low area, high resolution). FIG. 1 shows the generic two-step subranging architecture, comprising a reference ladder 104, a coarse ADC 102, a switching matrix 103, a fine ADC 105, coarse comparators 107, fine comparators 108 and an encoder 106. In most cases, a track-and-hold 101 is used in front of the ADC. In this architecture, an input voltage is first quantized by the coarse ADC 102. The coarse ADC 102 compares the input voltage against all the reference voltages, or against a subset of the reference voltages that is uniformly distributed across the whole range of reference voltages. Based on a coarse quantization, the switching matrix 103 connects the fine ADC 105 to a subset of the reference voltages (called a xe2x80x98subrangexe2x80x99) that is centered around the input signal voltage.
Modern flash, folding and subranging analog to digital converters (ADC""s) often use averaging techniques for reducing offset and noise of amplifiers used in the ADC. One aspect of averaging is the topology that is used to accomplish averaging, i.e., which amplifier outputs in which arrays of amplifiers are averaged together.
In general, flash, folding and subranging ADC""s use cascades of distributed amplifiers to amplify the residue signals before they are applied to the comparators 107, 108. These residue signals are obtained by subtracting different DC reference voltages from an input signal Vin. The DC reference voltages are generated by the resistive ladder (reference ladder) 104 biased at a certain DC current. Two implementation aspects of averaging that should be distinguished are circuit implementation and topology.
With respect to circuit implementation, various ideas have been published in the literature, e.g., connecting resistors between amplifier outputs, and connecting capacitors between amplifier inputs. Interpolation is a type of averaging, and additional published techniques include capacitive interpolation, active interpolation using differential pairs, active interpolation using current mirrors, and active interpolation using current splitting.
In general, little attention has been paid to the second aspect: the averaging topology. FIG. 2 shows an example of a conventional averaging topology. As may be seen from FIG. 2, three arrays of amplifiers are used to effect an averaging topology: an xe2x80x9caxe2x80x9d amplifier array, comprising amplifiers a1, a2, a3 . . . , a xe2x80x9cbxe2x80x9d amplifier array, comprising amplifiers b1, b2, b3 . . . , and a xe2x80x9ccxe2x80x9d amplifier array, comprising amplifiers c1, c2, c3. . . . The inputs of the xe2x80x9cbxe2x80x9d amplifiers combine several outputs of the xe2x80x9caxe2x80x9d amplifiers, and the inputs of the xe2x80x9ccxe2x80x9d amplifiers combine several outputs of the xe2x80x9cbxe2x80x9d amplifiers. Taking the b2 amplifier as an example, the b2 amplifier is connected to amplifiers a1, a2, a3, a4 through a summer SB2. Similarly, the amplifier c2 is connected to the amplifiers b2 and b3 through a summer SC2. The amplifier c2 therefore ultimately combines the outputs of the amplifiers a1, a2, a3, a4 and a5 through the amplifiers b2 and b3 and the summers SB2 and SB3. Because of this, the weights on the inputs (i.e., the weights on the outputs of the amplifiers a1 . . . a5) are not equal.
Averaging is needed to improve noise and offset performance of the amplifiers. Since the signals are correlated (i.e., add linearly) and the noise is uncorrelated (root mean square addition) the signal to noise ratio (SNR) at the xe2x80x9cbxe2x80x9d array of amplifiers is nominally unity for each xe2x80x9caxe2x80x9d amplifier, and {square root over ( )}4=2 for 4 amplifiers. The downside of this arrangement is that many connections are needed between the xe2x80x9caxe2x80x9d array and the xe2x80x9cbxe2x80x9d array. Another downside of this arrangement is the resulting different weighting coefficients, as discussed above, which detract from the root mean square additive property of noise.
The characteristic aspect of the topology of FIG. 2 is that averaging is ways performed on a set of neighboring amplifiers. For example, the amplifier b2 combines the outputs of the amplifiers a1, a2, a3 and a4, implementing 4xc3x97 averaging. The amplifier c2 combines the outputs of amplifiers b2 and b3, implementing 2xc3x97 averaging. Furthermore, the xe2x80x98averaging windowxe2x80x99 is optimized separately for each set of connections between two arrays of amplifiers. The averaging window may be considered a one-dimensional spatial filter. See Pan et al., IEEE J. of Solid State Circ. 36(12):1847-1858 (December 2001).
In most publications, the averaging window has an infinite width neglecting edge effects). This is an artifact of the circuit implementation used, i.e., averaging is implemented by connecting resistors between the amplifier outputs. An averaging window with a finite width can be obtained if different circuit implementations are used, e.g., active averaging or capacitive averaging.
In general, finite width averaging windows provide better performance, since they have a smaller edge effect, and they average only across amplifiers that are in their linear region. The disadvantage is that they require many connections between the amplifiers. For example, as shown in FIG. 2, each xe2x80x9cbxe2x80x9d amplifier requires connections to four xe2x80x9caxe2x80x9d amplifiers. This results in a considerable layout complexity, which can seriously degrade the ADC performance.
The present invention is directed to an analog to digital converter topology that substantially obviates one or more of the problems and disadvantages of the related art.
There is provided an analog to digital converter including a first amplifier array connected to taps from a reference ladder and to an input signal, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.
In another aspect of the present invention there is provided an analog to digital converter including a reference ladder connected to an input voltage, a first amplifier array connected to taps from the reference ladder, a second amplifier array connected to the first amplifier array in an interleaved manner, a third amplifier array connected to the second amplifier array in an interleaved manner, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal representing the input voltage.
In another aspect of the present invention there is provided an analog to digital converter including a reference ladder connected to an input voltage, a first plurality of amplifiers connected to taps from the reference ladder, a second plurality of amplifiers connected to the first plurality in an interleaved manner, a third plurality of amplifiers connected to the second plurality in an interleaved manner, and an encoder connected to outputs of the third plurality that converts the outputs to an N-bit digital signal representing the input voltage.
In another aspect of the present invention there is provided an analog to digital converter including a reference ladder, a plurality of amplifier arrays xe2x80x9caxe2x80x9d, xe2x80x9cbxe2x80x9d, xe2x80x9ccxe2x80x9d . . . xe2x80x9cnxe2x80x9d arranged in a cascade, wherein the amplifiers in the array xe2x80x9caxe2x80x9d are connected to taps from the reference ladder and to an input voltage, a plurality of connections between consecutive arrays of the plurality of amplifier arrays xe2x80x9caxe2x80x9d, xe2x80x9cbxe2x80x9d, xe2x80x9ccxe2x80x9d . . . xe2x80x9cnxe2x80x9d, wherein the connections are configured for maxc3x97mbxc3x97mcxc3x97. . . mnxc3x97 averaging of the taps, ma, mb, mc . . . mn representing an averaging factor of the corresponding amplifier array, and an encoder connected to outputs of the xe2x80x9cnxe2x80x9d amplifier array that converts the outputs to an N-bit digital signal representing the input voltage.
In another aspect of the present invention there is provided an analog to digital converter including a first amplifier array connected to taps from a reference ladder and to an input signal, a second amplifier array, wherein each amplifier in the second amplifier array is connected to at least two amplifiers of the first amplifier array, a third amplifier array, wherein each amplifier in the third array is connected to two at least two amplifiers of the second amplifier array, wherein an output of each amplifier of the first array has only one path to a corresponding amplifier of the third array, and an encoder converting outputs of the third amplifier array to an N-bit digital signal representing the input signal.
In another aspect of the present invention there is provided an analog to digital converter including a reference ladder, a plurality of amplifier arrays Ai, i=1 through n, arranged in a cascade, wherein the amplifiers in the array Ai are connected to taps from the reference ladder and to an input voltage, a plurality of connections between consecutive arrays of the plurality of amplifier arrays Ai, wherein each amplifier of each array Ai, i=2 through n, is connected to an output of a corresponding amplifier of an array Ak, k=1 through ixe2x88x921, through only one path, and an encoder connected to outputs of the An amplifier array that converts the outputs to an N-bit digital signal representing the input voltage.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.